(1) Field of the Invention
The present invention relates to a matched filter suitable for use in a radio receiver adopting direct sequence code division multiple access.
(2) Description of Related Art
In direct sequence code division multiple access (DS-CDMA [Direct Sequence Code Division Multiple Access]), the transmitter primarily modulates a data code in, for example, QPSK (Quadrature Phase Shift Keying), spreads a bandwidth thereof using a spreading code, and transmits the data code. On the other hand, the receiver cross-correlates using the same spreading code as in the transmitter to detect a peak of the correlation value, performs acquisition and tracking, and demodulates by correlation detection.
FIG. 11(a) is a block diagram of a transmitting unit of a radio terminal in DS-CDMA using QPSK. In the transmitting unit 30 of the radio terminal in DS-CDMA shown in FIG. 11(a), a data code is QPSK-modulated in a primary modulating unit 30a, a bandwidth of the signal is spread with an PN code (Pseudo Noise Code) in a spreading modulating unit 30b, an output of the spreading modulating unit 30b is up-converted in a frequency converting unit 30c, a power thereof is amplified in an RF amplifying unit 30d, and a radio signal is sent out to a radio propagation path from an antenna 30e. 
FIG. 12 is a diagram showing a relationship among a data code, a spreading code and a transmit code when the data is spread using QPSK in the primary modulation. Data codes Di and Dq are complex-multiplied by spreading codes Ci and Cq in multipliers 36a, 36b, 36c and 36d, and obtained results are added in adders 37a and 37b and outputted as transmit codes Si and Sq The complex-multiplication signifies an operation [(Di+jxc2x7Dq)xc2x7(Ci+jxc2x7Cq) with the date codes Di and Dq and the spreading codes CI and Cq, where j represents an imaginary unit (j2=xe2x88x921).
Next, a receiving system will be described. FIG. 11(b) shows a block diagram of a receiving unit of the radio terminal in DS-CDMA using QPSK. In the receiving unit 31 of the radio terminal in DS-CDMA, a weak radio signal whose bandwidth has been spread is received by an antenna 31a, the radio signal is amplified with a low noise in an RF amplifying unit 31b, an output of the RF amplifying unit 31b is down-converted in a frequency converting unit 31c. Further, the signal down-converted in the frequency converting unit 31c and a spreading replica code generated inside the receiving unit 31 are band-cross-correlated in a despread demodulating unit 31d, a narrow-band signal is thereby taken out, and an output of the despread demodulating unit 31d is QPSK-demodulated in a primary demodulating unit 31e. 
FIG. 13 is a diagram showing a detailed structure of the receiving unit 31 of the radio terminal in DS-CDMA using QPSK. As shown in FIG. 13, a flow of the signal in the frequency converting unit 31c, the despread demodulating unit 31d and the primary demodulating unit 31e is as follows. Namely, an I channel signal is mixed with an output of a local oscillator 38b in a frequency converting unit 38a, whereas a Q channel signal is mixed with an output of a 90xc2x0 phase shifter 38c in a frequency converting unit 38d. Outputs of the frequency converting units 38a and 38d are converted from analog to digital in A/D (analog/digital) converters 39a and 39b. These digital signals are branched and inputted to despread demodulating unit 40. In four matched filters in the despread demodulating unit 40, the signals are band-cross-correlated, an output of a matched filter 40a and an output of a matched filter 40d are added, in an adder unit 41a, whereby I channel data Si is outputted. In a similar manner, a signal obtained by inverting an output of a matched filter 40b and an output of a matched filter 40c are added in an adder unit 41b, Q channel data Sq is thereby outputted. These outputs are QPSK-demodulated in a post-demodulation processing unit 42.
Next, band-cross-correlation in the despread demodulating unit 40 will be described. The despread demodulating unit 40 generates spreading replica codes Ci and Cq in the same sequence as on the transmitter""s side to perform despreading, which comprises the matched filters 40a, 40b, 40c and 40d. When the two spread codes are cross-correlated, each of the I channel component and the Q channel component is despread two times, four times in total. In the matched filters 40a, 40b, 40c and 40d, M(nt) in the following formula (1) is computed.
M(nt)=xcexa3Tk=1R(k)xc2x7P(nt)xc2x7Zxe2x88x92kxe2x80x83xe2x80x83(1)
Where t is a chip duration, T is the number of taps, R is a spreading replica code, k and n are integers, P(nt) is a received spread code, and Z is a complex number in Z transform. One chip duration t represents a time for which the spread code is switched, designed to be a time of speed several tens to several hundreds times one bit duration. One chip duration t is a reciprocal of a chip rate. The number of taps T represents a length of a spread code. A length of the spread code is, for example, 256 bits, but there can be used a different spread code of, for example, 128 bits or the like. The received spread code P(nt) and the spreading replica code R(k) of 256 bits are EXORed, a result of this is shifted at the chip rate, added and outputted. Accordingly, an output signal Di of the A/D converter 39a and an output signal Ci of a spreading replica code generator 44a are cross-correlated in the matched filter 40a. In the similar manner, an output signal Di of the A/D converter 39a and an output signal Cq of the spreading replica code generator 44a are cross-correlated in the matched filter 40b, an output signal Dq of the A/D converter 39b and an output signal Ci of the spreading replica code generator 44a are cross-correlated in the matched filter 40c, and an output signal Dq of the A/D converter 39b and an output signal Cq of the spreading replica code generator 44a are cross-correlated in the matched filter 40d. A reason why the number of the matched filter is four is to-prevent degradation of an S/N (Signal/Noise) ratio of a despread signal.
Such a matched filter is a key device necessary to despread a received spread code, there is hence required a low power thereof. FIG. 14 is a diagram showing a block structure of the matched filter. The matched filter 40a (40b, 40c or 40d) shown in FIG. 14 cross-correlates a digital signal outputted from the A/D converter 39a or 39b shown in FIG. 13 with a spreading replica code generated inside the receiving unit 31, thereby despreading the signal. The matched filter 40a (40b, 40c or 40d) comprises a spread data path unit 43, a spreading replica code generator 44a, a register for replica code 44b, a multiplier unit 45 and an adder unit 46. The spread data path unit 43 is a shift register that captures a received spread code input at each clock and shifts the code one stage by one stage, which comprises T flip-flops (FF) 43-1, 43-2, 43-3, . . . 43-(Txe2x88x922), 43-(Txe2x88x921) and 43-T. Hereinafter, the flip-flop will be abbreviated as FF occasionally. The spreading replica code generator 44a generates a spreading replica code identical to one used in the transmitter. The register for replica code 44b is a register for computing the spreading replica code generated by the spreading replica code generator 44a. The multiplier unit 45 multiplies each of outputs of the flip-flops 43-1, 43-2, 43-3, . . . , 43-(Txe2x88x922), 43-(Txe2x88x921) and 43-T with each output of the register for replica code 44b. The adder unit 46 adds outputs from the multiplier unit 45 and outputs an added result. Each of the multiplier unit 45 and the adder unit 46 has the number of taps T, to which a clock at the chip rate is inputted. In FIG. 14, the number of spread data path bits represents the number of bits equal to a modulation multivalue in the primary modulation. In this case, the number of spread data path bits is 6. The received spread code signifies that one symbol is received with 6 bits. Therefore, a total number N of the necessary flip-flops is given by N=Dxc3x97T, where D is the number of spread data path bits and T is the number of taps of the flip-flops.
This circuit is an example where the number of times of over-sampling is 1, so that sampling is performed once during one chip duration. The flip-flops are therefore in T stages equal in number to a length of the spread code. When the over-sampling is performed plural times within one chip duration, the operation is performed plural times equal to the number of times of over-sampling within one chip duration. In the case of four-times over-sampling, for example, the sampling is performed four times within one chip duration on a spread code of 256 bits. The number of stages of the flip-flops M is given by M=Txc3x97O, where T is the number of taps T and O is the number of times of over-sampling. Accordingly, a total number N of necessary flip-flops is given by N=Dxc3x97M, where D is the number of spread data path bits and M is the number of stages of the flop-flops.
FIG. 15 is a functional block diagram of the matched filter. It is only necessary to hold a received spread code (spread data input) consisting of plural bits shown in FIG. 15 for one cycle in the sp read data path unit 43, it being unnecessary to shift the spread code. One cycle of the spread code is a time for which the received spread code is held, corresponding to a life time of P(nt). This cycle U is expressed as U=[(one chip duration)xc3x97(the number of taps T)]. The operation of the formula (1) is performed in the multiplier unit 45 and the adder unit 46, and can be performed in any portion without limitations on the order or positions of operators since the operation does not rely on results of operations performed before and after. Further, since the contents of the operation on any received spread code is quite the same, it is seen that the operation is xe2x80x9csymmetricalxe2x80x9d. With the matched filter, initial acquisition can be very quickly, and a process up to despreading can be completed once. The matched filter has futures {circle around (1)} through {circle around (4)} below.
{circle around (1)} operating at a frequency equal to or greater than a chip rate (in the case of over-sampling);
{circle around (2)} since the spreading data path unit is generally configured with a shift register, all the flip-flops always operate;
{circle around (3)} in order to certainly hand data to be shifted, a flip-flop of a master/slave type in two stages is used as the flip-flops configuring the shift register;
FIG. 16(a) is a diagram showing a structure of the shift register in which flip-flops of a master/slave type are used. FIG. 16(b) is a diagram showing an example of a structure of the flip-flop of a master/slave type in two stages. A clock terminal of the master FF and a clock terminal of the slave FF are given signals inverted to each other. FIG. 16(c) is a diagram for illustrating an operation of the flip-flop of a master/slave type in two stages. An input signal is stored at a posiedge clock, and the stored input signal is outputted at a negaedge clock shown in FIG. 16(c).
{circle around (4)} in the case of QPSK, four matched filters are basically required in order to separate into I channel and Q channel.
However, these futures conversely cause the following problems. Namely, these futures causes an increase of power consumption ({circle around (1)}) since the device operates at a high frequency, an increase of the number of flip-flops to be operated ({circle around (2)}), and an increase of circuit scale of the spread data path unit ({circle around (3)} and {circle around (4)}) further, from {circle around (2)} to {circle around (4)}, an increase of scale of the circuit because of the long shift register and adder. Moreover, since a switching activity in the spread data path unit is very high, the power consumption is increased.
Some of inventors of this invention have proposed a structure of a ring register in substance in the following publication.
Ben CHEN and Hideto FURUKAWA, xe2x80x9cA Low Power Consumption Digital Matched Filter Design for Wideband DS-CDMAxe2x80x9d, The Institute of Electronics, Information and Communication Engineers, 1998, xe2x80x9cTechnical Group of Circuits and Systems (CAS)xe2x80x9d Work Shop (Apr. 20 and 21, 1998).
FIG. 17 is a schematic block diagram of a matched filter 50 disclosed in the above publication. A received spread signal is stored in one of FFs in a spread data path unit 51b designated by a spread data input control unit 51a. Incidentally, the number of the FFs shown in FIG. 17 is equal to [(the number of taps)xc3x97(the number of times of over-sampling)]. A position designated by the spread data input control unit 51a is cyclically changed at each clock. The stored code is held in the register for only one cycle, shifting being not at all performed. In a multiplier unit 51c having multipliers having the same number [(the number of taps)xc3x97(the number of times of over-sampling)], a spreading replica code generated in its own station is shifted at each clock to perform EXOR operation, and a result of the operation is outputted from an adder unit 51d, whereby computation of despreading is completed.
FIG. 18. is a diagram conceptually showing circuit structures of the spread data input control unit 51a and the spread data path unit 51b, illustrating that circuit structures are conceptually ring. xe2x80x9cRingxe2x80x9d means that a position at which data is held in the spread data path unit 51b is cyclically changed. In other words, xe2x80x9cringxe2x80x9d means a cyclical circuit structure in which a received spread code is stored in a flip-flop at the tail of the shift register circuit, the next received signal is then stored in a flip-flop in the front of the shift register circuit. In this sense, the register circuit for storing (plural bits) is in a ring structure. Note that this does not mean a physical ring circuit arrangement.
FIG. 19 is a diagram showing a structure of the spread data input control unit 51a. A shift register circuit 52 shown in FIG. 19 is a circuit called a round robin ring, configured with [(the number of taps)xc3x97(the number of times of over-sampling)] flip-flops connected to one another. An output of a flip-flop at the tail of the shift register circuit 52 is inputted to a flip-flop at the head of the shift register circuit 52, so that the shift register circuit 52 is in the ring structure as well as the above circuit.
In the round robin ring, only one flip-flop indicates the state xe2x80x9c1xe2x80x9d, the remaining flip-flops are all kept in the state xe2x80x9c0xe2x80x9d, and the flip-flop in the state xe2x80x9c1xe2x80x9d is successively shifted at each sampling clock. Outputs of these flip-flops are connected to flip-flops of the spread data path register circuit 51b in the next stage, neither more or less. Only a flip-flop in the spread data path register circuit 51b connected to the flip-flop in the round robin ring whose state is xe2x80x9c1xe2x80x9d captures a received spread code. As this, a position in which a received spread code is stored is cyclically changed. In the spread data input control circuit 51a, a flip-flop in operation is always one, so that the switching activity is largely decreased, the power consumption is thus effectively decreased.
However, each of the spread data path register circuit 51b and the round robin ring (shift register circuit 52) is configured with flip-flops in 1024 stages simply connected to one another. For this, the circuit is excessively concentrated from a viewpoint of circuit structure or layout, so that the layout becomes impossible.
In the light of the above problems, an object of the present invention is to provide a matched filter, in which the spread data path unit is divided into sub spread data path units equal in number to the number of times of over-sampling so as to decrease a circuit scale of the spread data path unit, each of the sub spread data path units is configured with latch circuit so as to further decrease the circuit scale, each of the sub spread data path units uses an independent clock so as to decrease frequencies of circuit operation, a code load register always recognizes the leading position of a spread code so that the spread code can be instantaneously switched, and a dynamic mask is served to cope with a multi-tap spread code, whereby the switching activity and the circuit scale of the whole circuit of the matched filter is effectively decreased.
The present invention therefore provides a matched filter comprising a spread data path unit comprising a first selector being able to selectively output spread data, a plurality of sub spread data path units each comprising a plurality of latch circuits temporarily holding the spread data from the first selector, and a second selector being able to selectively output outputs from the sub spread data path units, a spread data path input control unit comprising a selector control unit for performing a selection control on the first selector and the second selector according to an input of the spread data, and a data holding control unit for performing a data holding control on the sub spread data path units, a spreading code setting unit being able to set a spreading code, and an arithmetic unit for multiplying an output from the spread data path unit by the spreading code from the spreading code setting unit, adding results of the multiplication and outputting a result of the addition.
Accordingly, with the above structure, the wiring becomes simpler, and excessive concentration of the circuits can be avoided. Since the huge spread data path unit is divided, not a high-speed clock but a low-speed clock can be used so that the power consumption can be decreased. Further, the switching activity and the circuit scale of the whole circuit of the matched filter can be effectively decreased.
The above spread data path unit may comprise sub spread data path units equal in number to the number of times of over-sampling, and each of the sub spread data path units may be configured with latch circuits equal in number to taps.
It is thereby possible to take out the contents at one clock, which is advantageous with respect to speed. It is also possible to reduce a scale of the whole circuit since a shift register causing an increase of the circuit scale is not used.
The data holding control unit may comprise a round robin ring in which finite-state holding units equal in number to the taps are arranged in a ring, and states of the finite-state holding units equal in number to the taps are successively changed at a chip rate such that a state of only one finite-state holding unit among the finite-state holding units equal in number to the taps differs from a state of the other finite-state holding units, so that data holding to the latch circuits configuring each of the sub spread data path units is updated in a predetermined order.
Accordingly, with the above structure, the layout becomes easy and wasteful switching can be avoided, since [(the number of times of over-sampling)xc3x97(the number of taps)] shift register circuit that is huge is not used.
The above selector control unit may comprise a phase counter for generating plural kinds of phase state signals within one chip duration and cyclically outputting the phase state signals, and the first selector may cyclically give inputted spread data to the sub spread data path units in synchronism with the different kinds of phase state signals from the phase counter, whereas the second selector may select one output among outputs of the sub spread data path units and output the selected output in synchronism with a corresponding one of the different kinds of phase state signals from the phase counter. The different kinds of phase state signals may correspond to phase states equal in number to the number of times of each over-sampling.
Accordingly, the layout of the circuit becomes easier, and wasteful switching can be avoided, since a huge shift register circuit is not used.
The above spreading code setting unit may set plural kinds of spreading codes in order to cope with plural kinds of spread code lengths. The spreading code setting unit may comprises code register for holding the spreading code for operation and a code load register being inputted thereto a control signal from the outside to load the next spreading code while the arithmetic unit operates, and the code load register may update contents at a predetermined position of the code register at a predetermined timing. The code load register may be inputted thereto an enable/disable signal controlled from the outside to capture the next spreading code when the enable/disable signal is enable, while not capturing when the enable/disable signal is disable, and be controlled by an algorithm updating contents at the leading position of the code register in synchronism with the code register.
Accordingly, with the above structure, it is possible to cope with an instantaneous switching of the spread code even if the spread code or the number of taps in use is changed.
The above spreading code setting unit may comprise a code register for holding the spreading code for operation and a code load register being inputted thereto a control signal from the outside to load the next spreading code while the arithmetic unit operates, a multi-tap control unit may be disposed on the multiplied output""s side of the arithmetic unit in order to cope with plural kinds of spreading codes, the multi-tap control unit may comprise a mask ring comprising finite-state holding units not less in number than applied taps, and a logical product of an output of each of the finite-state holding units of the mask ring and a multiplied output of the arithmetic unit is outputted to an adder unit of the arithmetic unit.
Accordingly, with the above structure, it is possible to cope with different kinds of spread code lengths with one matched filter, so that it is possible to track the data even if an optional specification is added to the system, and a degree of freedom in designing is increased.
In the mask ring, continuing finite state holding units equal in number to the taps among the finite-state holding units may hold the same state so that a state thereof differs from a state of the other finite-state holding units, and the leading position in the mask ring may be shifted in synchronism with the code register. The multi-tap control unit may be inputted thereto a spread code identify signal that can be controlled from the outside.
Accordingly, with the above structure, the leading position in the mask rings is shifted in synchronism with the code register so that data tracking is possible.
The present invention also provides a matched filter comprising a spread data path unit comprising a plurality of sub spread data path units in each of which a plurality of latch circuits are arranged in order that spread data is inputted thereto, a spread data path input control unit for performing a data holding control to the latch circuits, in a predetermined order according to an input of the spread data, a spreading code setting unit being able to set a spreading code, and an arithmetic unit for multiplying an output from the spread data path unit by the spreading code from the spreading code setting unit, adding results of the multiplication and outputting a result of the addition.
Accordingly, with the above structure, the wiring becomes simple and excessive concentration of the circuit can be avoided, as well. Since the hug spread data path unit is divided, it becomes possible to use a low-speed clock in lieu of a high-speed clock, which leads to a decrease of frequencies of the circuit operation. Further, the switching activity and the circuit scale of the whole circuit of the matched filter are effectively decreased.